Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer Design Methodology
Prof Dr Chua-Chin Wang
Date: 4 November 2019 ( Monday )
Time: 1.30pm – 4.00pm
Venue: Auditorium 1, Level 1, Kompleks Eureka, Universiti Sains Malaysia, 11800 USM Pulau Pinang
Ever since the reliability issues caused by I/O (input/output) compatibility among chips fabricated using different processes were raised by cellular phone makers during mid-2000, on-silicon mixed-voltage I/O buffer with wide voltage tolerance was considered better solution than using signal-level converters to shrink PCB size, number of discrete components, and power consumption. However, various external voltages on I/O pad result in body effect, leakage, hot-carrier degradation, and gate-oxide overstress in stacked transistors of mixed-voltage I/O. What even worse is that slew rate (SR) was also found deteriorated by PVT (process, voltage, temperature) variations. Therefore, many design techniques for CMOS mixed-voltage I/O buffer design using nano-scale CMOS processes will be introduced and analyzed, including clamping dynamic gate bias generator, dynamic biasing, and leakage detection, such that these I/O buffers will be able to transmit and receive digital signal with 2x or even 3x VDD voltage swing. The reliability design consideration for the digital I/O buffers, including ESD, PVT detection, and slew rate (SR) auto-adjustment will also be discussed as well. The maximum data rate can be drastically enhanced to meet the latest I/O interfacing protocol requirements.
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