|University / Institute||Universiti Putra Malaysia|
|Project Title||Modeling and Cross-Layer Power Optimization in Standard Cell Library Design for SoC Application|
|Contact Name / Email(s)||Fakhrul Zaman Rokhani / firstname.lastname@example.org|
|Nationality Requirements on Candidate(s)||Applicants must be Malaysian citizens|
|Description||The major challenge in designing next-generation System-on-Chip (SoC) has been shifted from ‘absolute timing’ to ‘meeting timing without blowing out the power budget’. In this project, cross-layer power optimization on standard cell library is proposed to aggressively mitigate both dynamic and leakage power of SoC chips. Prototype standard-cell libraries will be designed on industry standard process and test-chips will be fabricated for several SoC chips to validate the effectiveness of the approach.
The GRA candidate is expected to design a functional image/video signal processing codec in synthesizable RTL and performs physical design in two stages – FPGA board and ASIC using the optimized standard cell library. Research contributions can be in the form of (but not limited to) codec architecture optimization, algorithm optimization, power efficient design based on approximate computing concept and others.
GRA Vacancy : Research on Cell Library Design for SoC Application
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