GRA position at USM – Master – Formulation of a noise model for a 0.13-μm CMOS transistor

[IEEEMY] Fwd: GRA position at USM

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zuhaina zakaria via listserv.ieee.org

Mar 24 (5 days ago)

Another GRA opportunity…
Interested applicants can contact Dr. Norlaili Binti Mohd. Noh by email at eelaili@usm.myPlease state “RUI GRA Application” as the subject of the email.Include latest resume/CV.Shortlisted candidates will be contacted.

Best Regards,
Zuhaina Zakaria, PhD, SMIEEE, MIETChair IEEE Malaysia Section
Deputy DeanInstitute Graduate StudiesUniversiti Teknologi MARA,Malaysia

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No. Matter Details
1 Project Title Formulation of a noise model for a 0.13-μm CMOS transistor with emphasis on geometry, dc biasing, layout and frequency variations

 

2 Source of Funding Individual Research University Grant

 

3 Project Duration 2 years

 

4 Monthly Allowance RM 1800.00 (Master)

 

  Location School of Electrical & Electronic Eng., Engineering Campus USM, NibongTebal

 

5 Project Summary Noise behavior of CMOS transistors with respect to variation in geometry, DC biasing, layout and also frequency is investigated. The focus of this project is to study on the thermal and flicker noise behavior and their relationship to all of the varying parameters described above. In addition, noise trends corresponding to the difference in layout techniques will also be looked into. The target of this project is to create an accurate noise model that is able to predict accurate noise level at various configurations. Achieving accurate noise model will ensure the first time silicon success in integrated circuit. It will also indirectly create confidence amongst the multinational semiconductor investors in the local talents of IC designers.

 

6 Requirements
  1. B.Eng. in Electronic Engineering with a CGPA of 3.0 and above
  2. proactive and able to carry out research independently

 

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