Short Course on VLSI System Modelling and Test | 24 Dec 2013

Centre for Intelligent Signal and Imaging Research (CISIR) of Universiti Teknologi Petronas is organizing 1 day short course on “VLSI SYSTEM MODELLING AND TEST”, to be held on 24 December, 2013 at Centre for Intelligent Signal and Imaging Research (CISIR), Universiti Teknologi PETRONAS. This short course is co-organised by IEEE CAS Malaysia Chapter.


The course will cover an overview of electronic testing, automated model gen-eration for high level fault modelling (HLFM), system level testing for complex system-on-chips including design-for-testability and core-based test scheduling. The topics of logic built-in self-test (LBIST) will also be covered, with an exam-ple LBIST implementation case study looking at several low power techniques. Participants will get an opportunity to have hands-on experience on high-level automated model generation using software provided from Mentor Graphics.


Important Dates:

Short Course Date: 24 December, 2013

Registration Deadline: 20 December, 2013

For accommodation in UTP Hostel: 18 December, 2013



NOTE: Seats are limited and a seat will be reserved once the payment is received along with the scan copy of registration form attached in the brochure.


Confirmation upon receiving scan copy of Registration Form and Cheque/pay order to one of below emails:



For the further inquiries, kindly contact Mr. Dileep Kumar (Research Scientist), UTP Malaysia


Email: or

H/P No.: 0195591650


You are kindly requested to extend the short course information to your colleagues/students who are working on the VLSI/Embedded System/Modeling.


Thank you for your kind attention and cooperation.


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