Tutorial SessionDateTime
Tutorial 1Nov 22, 202009:00 – 12:00
Tutorial 2Nov 22, 202013:00 – 16:00

Tutorial 1

Date/Time: Nov 22, 2020, 9:00 am – 12:00 pm

Prof. Shi-Yu Huang

Professor, Faculty of Electrical Engineering Department,
National Tsing Hua University, Taiwan.

Testing Power and Clock Networks


Power and Clock distribution networks are important lifelines of an IC. Parametric defects on them could cause mysterious functional failures. However, they have been mostly overlooked in a traditional test flow so far. In this tutorial, we discuss a few recently developed practical and effective methods to cover up this void. Instead of wondering what may have gone wrong when there is a performance glitch or functional failure, we can now choose to simply check out the health condition reports produced by these methods, to figure out what may have actually happened in silicon.

In the first half, we will discuss how to apply all-digital timing circuits (such as ring oscillator, Time-to-Digital Converter, Phase-Locked Loop, etc.), to form the test infrastructure for the monitoring of the ellusive short-time dynamic VDD drops, while taking into account the temperature effects. In the second half, we will focus on a non-intrusive “modified flush test procedure” that can provide fine-resolution multi-level test results for small delay faults occuring to the clock network. The circuit techniques to realize the on-chip test clock generator will be addressed as well. At the end of the tutorial, we hope that the auidence can experience how powerful a test paradigm can become when we start to explore another dimension that incorporates some easy-to-design timing circuits into our overall test infrastructure.


Shi-Yu Huang received his Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara, in 1997. He joined the faculty of Electrical Engineering Department, National Tsing Hua University, Taiwan, in 1999, where he is currently Professor. His research interests broadly cover VLSI design, automation, and testing, with prior experiences on formal verification, power estimation, fault diagnosis, and resilient nanometer SRAM Design. More recently, his research is concentrated on all‐digital timing circuit designs, such as all‐digital phase‐locked loop (PLL), an all‐digital delay‐locked loop (DLL), time‐to‐digital converter (TDC), and their applications to parametric fault testing and reliability enhancement for 3D‐ICs. He has published more than 155 refereed technical papers. Prof. Huang co‐founded a company, TinnoTek Inc. (2007‐2012), specializing in a cell‐based PLL compiler and system‐level power estimation tools. He received the best‐presentation or best‐paper awards from VLSI-DAT’06, VLSI-DAT’13, ATS’14, WRTLT’17, and ISOCC’18, respectively. Dr. Huang has actively served in the IEEE community, as Program/General Chairs/Co-Chairs in several IEEE technical conferences, including ATS, MTDT, VLSI-DAT, ITC-Asia, and Associate Editor for IEEE Trans. on Computers from 2015 to 2018.

Indended Audience:
  • Test practitioners who are involved in designing test architectures and circuits to facilitate the online testing or monitoring of delay faults or parametric defects occurring to the power/clock delivery networks.
  • Students or researchers who plan to develop powerful test paradigms for detecting parametric faults occurring anywhere in the IC by incorporating more and more popular all-digital timing circuits.

Tutorial 2

Date/Time: Nov 22, 2020, 13:00 pm – 16:00 pm

Prof. Adit Singh,

James B. Davis Professor,
Electrical & Computer Engineering,
Auburn University, AL, USA.

Mr.Andreas Glowatz

Principal Engineer & Software Architect,
Mentor Graphics, Siemens, Germany.

Critical Area Guided Test Selection For Automotive Applications


New defect types and failure modes observed in advanced technology nodes are leading to the development of advanced fault models for test generation that exploit both cell layout and circuit timing information. However, not all the new tests generated by these models can be indiscriminately added to the test set because of unacceptable increase in test pattern count. Choices must be made to stay within the test time budget. Traditionally, test selection has been based on the fault coverage of the patterns in simulation, but this does not necessarily reflect fault criticality and actual defect coverage in silicon. New test tools from industry are exploiting design-for-manufacturing (DFM) data and layout-based defect critical area analysis to more accurately prioritize the effectiveness of tests. The new methodology is presented in detail in this tutorial.


Adit Singh is James B. Davis Professor of Electrical and Computer Engineering at Auburn University, where he has served on the faculty since 1991. Earlier he has held faculty positions at the University of Massachusetts in Amherst, and Virginia Tech, in Blacksburg; and visiting professorships at the University of Freiburg, Germany, and the University of Tokyo, Japan.  His research interests span all aspects of VLSI technology. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing.  Dr. Singh has held leadership roles as General Chair/Co-Chair/Program Chair for dozens of VLSI design and test conferences, and continues to serve on the Steering and Program Committees of many major international conferences in test and design automation. He served two terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and (2011-2015) on the Board of Governors of the IEEE Council on Design Automation (CEDA). Dr. Singh holds a B.Tech in Electrical Engineering from IIT Kanpur, and the M.S. and Ph.D. from Virginia Tech. He was elected Fellow of IEEE in 2002.

Andreas Glowatz is Principal engineer and head of the research and development department at Mentor, A Siemens Business in Hamburg, Germany. He received his diploma in Electronics and Computer Science 1988 from University of Applied Sciences in Hamburg, Germany. He has over 30 years of experience in R&D of DFT tools with the main focus on ATPG, test compression, and Cell-Aware test. He holds several patents and is co-author of many publications.