Keynote Speaker 1

Dr. Yervant Zorian

Synopsys Fellow & Chief Architect

Title: Robustness Challenges in the Internet of Things

Abstract:

The Internet of Things (IoT) is an extremely fragmented market and can be defined as anything from sensors to small servers. It is estimated that over 30 billion IoT devices will ship this year. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications, such as in wearable devices (for health, fitness or infotainment applications) and in machine-to-machine applications (in smart appliances, smart cities or commerce).  It has become crucial for today’s IoT chips to use a range of new solutions during the design stage to ensure the robustness of manufacturing test, field reliability and security. DFT designers need to use new test and reliability solutions to enable power reductions during test, concurrent test, isolated debug and diagnosis, pattern porting, calibration, and uniform access. Moreover, the per unit IoT price remains a key factor in high volume production. Thus, minimizing the test cost while meeting the above technical issues is one of the major challenges of the IoT industry. This presentation, besides discussing the key trends and challenges of IoT, will cover solutions to handle the wide range of potential robustness challenges during all periods of the IoT lifecycle from design, post silicon bring-up, volume production, to especially in-system operations.

Biography:

Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.

Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia’s National Medal of Science.

He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.


Keynote Speaker 2

Prof. Dr. Said Hamdioui

Chair Professor, Head of Computer Engineering Laboratory
Delft University of Technology
Co-Founder and CEO of Cognitive-IC

Title: Computation-In-Memory Architectures based on NV devices: Opportunities and Challenges

Abstract:

Emerging applications are extremely demanding in terms of storage, computing power and energy efficiency. On the other hand, both today’s computer architectures and device technologies are facing major challenges making them incapable to deliver the required functionalities and features at economical affordable cost. In order for computing systems to continue deliver sustainable benefits for the foreseeable future society, alternative computing architectures and notions have to be explored in the light of emerging new device technologies.

This talk addresses the potential, design, and test of Computation-in-memory architecture based on non-volatile (NV) devices such as ReRAM, PCM and STT-MRAM. First, the talk briefly explains the limitation of both CMOS scaling and today’s computing architectures. Then it classifies the sate-of-the art computer architectures and highlight how the trends is going toward computation-in-memory (CIM) architectures in order to eliminated and/or significantly reduces the limitations of today’s technologies.  The concept of CIM based on NV devices is discussed, and logic and arithmetic circuit designs using such devices and how they enable such architectures are covered; data measurements are shown to demonstrate the CIM concept in silicon. The strong dependency of application domains on the selection of appropriate CIM architecture and its building block, as well as the huge potential of CIM (in realizing order of magnitude improvement in terms of computing and energy efficiency) are illustrated based on some case studies. Moreover, the testing of new non-volatile memories enabling CIM as well as testing of CIM are discussed; it will be demonstrated that traditional approach for fault modeling and test development is incapable to deal with realistic defects in emerging CIM devices (e.g., ReRAM and STT-MRAM based), and a new approach called Device Aware Test (DAT) will be covered. Industrial data are presented to show that DAT sensitizes realistic faults as well as new unique defects and faults that can never be caught with the traditional approach. Finally the research directions in different aspects of computation-in-memory are highlighted.

Biography:

Hamdioui is currently Chair Professor on Dependable and Emerging Computer Technologies, Head of the Computer Engineering Laboratory (CE-Lab), and also serving as Head of the Quantum and Computer Engineering department of the Delft University of Technology, the Netherlands. He is also co-founder and CEO of Cognitive-IC, a start-up focusing on hardware dependability solutions. Hamdioui received the MSEE and PhD degrees (both with honors) from TUDelft. Prior to joining TUDelft as a professor, Hamdioui worked  at Intel Corporation (Califorina, USA), at Philips Semiconductors R&D (Crolles, France) and at Philips/ NXP Semiconductors (Nijmegen, The Netherlands). His research focuses on two domains: Dependable CMOS nano-computing (including Testability, Reliability, Hardware Security) and emerging technologies and computing paradigms (including memristors for logic and storage, in-memory-computing, neuromorphic computing, etc).

Hamdioui owns two patents, has published one book and contributed to the other two, and over 200 conference and journal papers. He has consulted for many worldwide semiconductor companies in the area of hardware dependability. He is strongly involved in the international community as a member of organizing committees (e.g., general chair, program chair, etc) or a member of the technical program committees of the leading conferences. He delivered dozens of keynote speeches and invited lectures and tutorials at major international forums/conferences/schools and at leading semiconductor companies. Hamdioui is a Senior Member of the IEEE, has served on the editorial board of may journals (TVSI, D&T, ACM ETCS, JETTA, etc). He is a member of the AENEAS/ENIAC Scientific Committee Council (AENEAS =Association for European NanoElectronics Activities). Hamdioui is the recipient of many international/national awards including European Design Automation Association Outstanding Dissertation Award 2003, many Best Paper Awards (e.g., DATE 2020, LATS 2018, FCST 2017, IVLSI 2016, ICCD 2015, etc), the 2015 HiPEAC Technology Transfer Award, Teacher of the Year Award 2017 at the faculty of Electrical Engineering, Delft University of Technology, the Netherlands; etc.


Keynote Speaker 3

Mr. Kam Heng Lee

Vice President & General Manager, Intel Manufacturing Product Engineering (Malaysia) and High-Volume Engineering

Title: Manufacturing and Test Challenges for Products with Heterogeneous Silicon Integration

Abstract:

Heterogeneous integration of different silicon on an advanced package has become an increasingly important strategy for companies to deliver competitive product. Integrating all different intellectual properties (IPs) in a monolithic die at advanced silicon technology node is very costly. It not only requires a lot of resources to move all IPs to the latest technology node, it also takes longer time and will grow the die size, all of which leads to higher overall investment. To overcome these issues, companies are now adopting the strategy of heterogeneous integration, i.e. integrating different silicon from different sources onto a multi-chip package. This is made possible with advancement in the packaging technology, allowing silicon to be integrated in two-dimensional or three-dimensional fashion without major performance loss due to interconnects. It allows the design teams to quickly mix and match the IPs to deliver the best performance.

However, this heterogeneous integration technique present significant challenges to manufacturing and test. The back-end manufacturing flow is significantly more complex than before. This presentation will discuss the heterogeneous integration advancement made by Intel, the corresponding challenges to manufacturing and test, and offer some thoughts for considerations when dealing with heterogeneous integration.

Biography:


Kam Heng Lee is a vice president and general manager of Malaysia Manufacturing Product Engineering and High-Volume Engineering at Intel Corporation. Lee manages the global High-Volume Engineering with groups in Malaysia, China, Vietnam, and Costa Rica. Lee also serves as General Manager of Malaysia Volume Lab Engineering and Manufacturing Product Engineering at the Malaysia site. The team develops and delivers competitive product manufacturing test solutions across a wide range of products. Lee first joined Intel in 1995 and has held a successful career in technology development and product engineering. Prior to his current role, Lee was director of New Product Integration in Assembly Test Manufacturing (ATM), where he was responsible for new product integration, new process technology deployment, A/T process yield integration, and A/T OpX in the ATM factories network. Earlier in his career at Intel, Lee held the position of Malaysia site director for Assembly Test Technology Development. In this role, Lee was chartered to develop test technologies to support future Intel products.