An industry forum addressing the question of “How significant is the need for Design For Testability in IOT Devices Solution?” is scheduled on Wednesday, 25th November 2020.

The panelist of this forum is as below:

Forum Panelist

Moderator: Professor Virendra Singh, Indian Institute of Technology, Bombay

Panelist:
1) Visiting Professor Yasuo Sato, Kyushu Institute of Technology, Japan
2) Dr. Rubin Parekhji, Texas Instruments, India
3) Dr. Zhigang Jiang, Marvel, USA.

Biographies of Panelist:

Yasuo Sato received the M.S. degree in mathematics from Tokyo University, and Ph.D. in engineering from Tokyo Metropolitan University. He was in Hitachi, Ltd. working in computer-aided design. He was a senior manager of DFT (Design for Testability) group at the Semiconductor Technology Academic Research Center (STARC). He was a research professor in the Department of Computer Science and Electronics, Kyushu Institute of Technology from 2009 to 2013, and is currently is a visiting professor. He is also being a researcher at the University of Electro-Communications from 2017. His particular interest area includes LSI Design for Technology and RF Energy Harvesting. Dr. Sato is a member of the IEEE and IEICE.

Rubin Parekhji has been with Texas Instruments, Bangalore, since 1996, where he has led and mentored DFT teams on various design and test technology projects across multiple product groups. More recently, he has been in Kilby Labs and Analog Engineering Operations / Central Analog Engineering at TI, working on low cost test methods and test entitlement targets with world-wide teams, as a distinguished member of the technical staff. He has published regularly and delivered tutorials at leading conferences, has mentored a large number of students, and has several issued patents. He has a Ph.D. from Indian Institute of Technology, Bombay, India.

Zhigang Jiang received the B.S.E.E degree from Tsinghua University, M.S.E.E from San Jose State University, and Ph.D. from University of Southern California. He was in SynTest Technologies, leading ATPG tool development from 2004 to 2011. He is currently in Marvell, working on DFT design in the SOC design group. His particular interest area includes Design for Testability, and Design Automation.